CONTINUATION OF ABOUT UART

UART STANDARD SERIAL DATA FORMAT:

Standard UART characters are contained within frames consisting of start/stop indicators, data, and parity information. The serial bit stream uses the following sequence:

·         Start bit

·         Data bits

·         Parity bit (if enabled)

·         Stop bit(s)

When there is nothing to be sent, the serial line is high. The first low bit is the start bit, which indicates the beginning of a new frame. The next five to eight bits are data bits, which convey the actual information to be sent, least significant bit first. The number of data bits per frame is configurable. If enabled, a parity bit will be sent on the serial line after the data bits. Finally, the serial line is held high again for at least one bit to indicate the end of a frame. This is called the stop bit, which also returns the serial line to the idle state. The type of parity and length of stop bits are also configurable. 

UART MODULE DESCRIPTIONS:

The UART core consists of five modules:

• Transmitter

• Receiver

• Modem interface

• Baud generator

• Interrupt controller

 UART TRANSMITTER

To send data with the UART, the processor writes data to the transmitter address as if it was a memory space. The transmitter controls the entire transmission process. The transmitter performs parallel-to-serial conversions, and sends data on the serial line. The processor pushes data (5 to 8 bits wide) into the transmit FIFO, which is 256 bytes deep. The transmitter pops the data off the FIFO, and shifts it out at the baud rate. The Divisor Registers determine the baud rate. Using the Line Control Register, the user can configure the number of data bits (5, 6, 7, or 8) per frame, as well as the number of stop bits (1, 1.5, or 2) to be sent at the end of a frame. The transmitters also has a parity generation circuit that is capable of creating even, odd, stick even, or stick odd parity. When parity generation is disabled, no parity will be sent after the data bits.

There is one interrupt associated with the transmitter—it is a third-level priority interrupt that occurs when the transmit FIFO is empty.

Logically, the transmitter performs the following steps:

1. If there is data available in the FIFO, loads a byte into the shift register.

2. Sends a start bit on the serial line, indicating the beginning of a frame.

3. Shifts out data bits from the shift register to the serial line.

4. If parity is enabled, sends a Parity Bit after all data bits are sent.

5. Sends stop bit(s) on the serial line, indicating the end of a frame.

UART RECEIVER

To receive data with the UART, the processor reads data from the receiver address as if it was a memory space. The receiver is responsible for capturing data from the serial line and validating data integrity. The receiver performs serial-to-parallel conversions, and pushes data into the receive FIFO at the baud rate. The processor can pop data from the 256-byte deep receive FIFO at the system clock frequency. The supplied RCLK must be 16 times faster than the baud rate. The receiver monitors the serial line. When a valid start bit is detected, the receiver begins to shift data bits from the serial line, and saves the received data in the receive FIFO.Using the Line Control Register, the user can configure the number of data bits (5, 6, 7, or 8) per frame, as well as the type of parity to expect on the serial line. The receiver has a parity generation circuit that is capable of creating even, odd, stick even, or stick odd parity as data is shifted in from the serial line. The calculated parity is then checked with the received parity to determine data integrity. When parity generation is disabled, no parity will be expected after the data bits.

Besides parity errors, the receiver is also capable of detecting frame errors, overrun errors, and break errors. Frame errors occur when the receiver is expecting a stop bit but received a '0' on the serial line. Overrun errors occur when they receive FIFO is full and the newly received data is destroyed because it cannot be saved in the FIFO. Break errors occur when the serial line is '0' for more than a full frame. Break errors, frame errors, and parity errors are associated with the particular pieces of data in the FIFO that contains the errors. LSR indicates if there are any errors in the entire receive FIFO.In addition to error detection capabilities, the receiver also features false start bit detection and self-recovery from frame error. The serial line may be subject to noise, so it is essential that the receiver be able to differentiate noise from a valid start bit. For the receiver to recognize a '0' on the serial line as a valid start bit, this '0' value must remain for at least half a baud cycle from the falling edge of the serial input. If the start bit does not remain stable in that period, it is discarded and the receiver will return to its idle state. The asynchronous nature of a serial line means it is possible that the receiver is out of synch from the transmitter, resulting in a frame error. When a frame error occurs, the receiver tries to resynchronize itself to the transmitter. To achieve this self-recovery feature, the receiver assumes that the invalid stop bit is actually the start bit of the next frame, and proceeds to shift in data bits from the serial line.

There are three interrupts associated with the receiver. The highest-level priority interrupt occurs when the received data has an error. A second-level priority interrupt occurs when they receive FIFO has reached its trigger level. Another second-level priority interrupt is the timeout interrupt, which occurs when data is sitting idle in the receive FIFO for over a certain period of time. 

To perform all these functionalities, the receiver performs the following steps:

1. Hunts for a valid start bit, which indicates the beginning of a frame.

2. Shifts in data bits from the serial line to the shift register.

3. If parity is enabled, compares received parity bit with the expected value.

4. Checks for a valid stop bit on the serial line, which indicates the end of a frame.

MODEM INTERFACE

The modem interface allows the processor to transmit data to another terminal, or handshake to the modem input signals. It also makes the modem's status available to the processor. The Modem Status Register reports status information in two ways. It shows the values of DCDn, Rin, DSRn, and CTSn signals from the modem, and it also indicates whether any of those signals have changed since the last time it was read by the processor. The user can drive the values of OUTn1, OUTn2, RTSn, and DTRn via the Modem Control Register. 

BAUD GENERATOR

The baud generator is capable of creating a clock by dividing the system clock by any divisor from 2 to 216-1. The divisor is the unsigned value stored in the Divisor Register. The output frequency of the baud generator is 16 times the baud rate. This means, the Divisor Register must hold a value equal to the system clock divided by baud rate and further divided by 16. This output clock can be used as the receive reference clock by the receiving UART.

  

INTERRUPT CONTROLLER

The interrupt controller works with the transmitter, receiver, and modem interface to notify the processor of events that require intervention. The user can configure which interrupts to enable or disable via the Interrupt Enable Register (IER). When the processor is interrupted, it can find out more details regarding the interrupt by reading the Interrupt Identification Register (IIR).The interrupt controller monitors internal interrupt request lines from other modules. These internal interrupts are masked with the IER. The interrupt controller is then able to determine the interrupt pending with highest priority, and report it in the IIR. After the interrupt has been serviced, the interrupt controller clears the interrupt request and updates the IIR accordingly.