DESCRIPTIONS OF DIFFERENT ICS 2

5. Input offset voltage     ------------   1.0 mV.

6. Input Bias current         ------------   80 nA.

7. PSSR          --------------               30 mV/V.

8. Input resistance    -------------         2MW.

9. CMMR         --------------                90.

10.  Output resistance         ----------      75W.

11.  Bandwidth          -----------              1.0 MHz.

   12.  Slew rate            ------------              0.5 V/m sec.

  LM 311N Voltage Comparator

 

1. Total supply voltage          ------------      36 V

2.  Input Voltage       -------------                ±15V

3. Power dissipation         ------------      500mW 

4. Operating temperature  ---------  0⁰ C to 70⁰C

5. Input offset voltage         ---------         2.0 mV

6. Input Bias current     -----------             100 nA

7. Voltage gain     ----------------           200V/mV

NE / SE 555 / SE 555C

1. Supply voltage            ------------          4.5 V to 18 V

2. Supply current             -------------                      3mA

3. Output voltage (low)        ---------------             0.1 V

4. Output voltage (high)         --------     12.5 V (15 V Vcc) & 3.3 V (5V Vcc)

5. Maximum operating frequency                      ------------           500 KHz

6. Timing from m sec to hours

VCO IC 566

1. Operating supply voltage (V_cc)    ---------     12V (on less otherwise specified 24V).

2. Operating Supply current        --------------      12.5 m.A.

3. Input Voltage (V_c)             --------------                 3V_p-p.

4. Operating Temprature       ------------             0 to 70⁰C.

5. Power dissipation                ------------          300Mw.

Phase Locked Loop NE / SE 565 

 

1. Maximum supply voltage        -----------      26 V

2. Input Voltage          ----------------         3 V(P-P)

3. Power dissipation          -------------       300Mw

4. Operating temperature    -----   NE 565- 0⁰ C to 70⁰C (SE 565—55 to +125⁰ C

5.  Supply voltage        -----------               12 V

6. Supply current        ------------              8 mA

7. Output current- (sink)             -------     1 mA

                              (Source)    ----------      10 mA

IC 723 Voltage Regulator

 

1.Input voltage       -----------            40V max.

2.Output voltage      -----------      2V  to  37V.

3.Output current            -----------       150mA .

    (With out external pass txt)

4.Output current      -------------               10A.

   (With external pass txt)

5.Input regulation      ---------------      0.02%.

6.Load regulation    ---------------      0.03%.

      7.Operating temperature       ------     55⁰ C  to  125⁰ C.

Three Terminal Voltage Regulators  

 

IC 7805

 

1.Input voltage (5V trough 18V)    -------       35V.

                       (24V)     ----------                   40V.

2.Internal power dissipation    -------    Internally limited.

3.Storage temperature  range    --------       -65⁰ C  to  150⁰ C.

4.Operating junction

       Temperature range

                            mA7800         ---------     -55⁰ C  to  150⁰ C.

                            mA7800C       --------        0⁰ C  to   125⁰ C.

IC 7905

 

1.Input voltage (5V trough 18V)    -------      -35V.

                     (24V)     ----------                   -40V.

2.Internal power dissipation    -------    Internally limited.

3.Storage temperature  range    --------       -65⁰ C  to 150⁰ C.

4.Operating junction

       Temperature range

                            mA7800         ---------      -55⁰ C  to 150⁰ C.

                            mA7800C       --------       0⁰ C  to   125⁰ C.

IC LM35

 1. Popularly named as temperature sensor

 2. Power supply or supply voltage ----------- 5V

 3. Output Volatage ------------- 6V

 4. Ground ---------0V

 5. Three pin IC Vcc, Ground, Output

PHASE LOCKED LOOP LM565

Phase Locked Loop (PLL) is a versatile electronic servo-system that compares the phase and frequency of a given signal with those of an internally generated reference signal. PLL has emerged as one of the fundamental building block in electronic technology. It is used for the Frequency Multiplication, FM stereo detector, FM Modulator, frequency shift keying decoders, local oscillator in TV and FM tuner. PLLs can be used at relatively high frequencies, with geneneral purpose PLLs available for use up to about 10MHz and more expensive, specialized PLLs available for higher frequencies. Pacific educational trainer AET-26 is a useful kit for the demonstration of Phase Locked Loop characteristics like. Lock range; capture range and Free running frequency. This consists of: 

1.      Regulated power supplies (+12v and + 5v).

2.      Square wave generator.

3.      Phase Locked Loop circuit using LM565.

1.Regulated Power Supplies ( +12v and + 5v ):

                 

              This consists of Bridge rectifier followed by capacitor filters and three terminal regulators to provide +12v and + 5v regulated DC voltages @ 200mA each. These supplies are internally connected to the circuits where is required, so need of an external connections. Test points are provided in the circuit to measure (verify) respective voltages.

2.Square Wave Generator:

                  A Square Wave Generator of 1KHz to 10KHz is provided to use as input signal to the PLL. Voltage Controlled Oscillator 565 is used here as an active component. A 10 turn potentiometer (also called as “helipot”) is used in order to get high resolution (fine adjustment) in loading effect from the PLL circuit. A separate output control is provided to vary the output amplitude.

3.Phase Locked Loop circuit Using LM565:

                   The LM565 from National semiconductor is a 14-pin IC that can be connected to external components to form a PLL. Figure 1.1 shows a PLL circuit diagram using 565. Differential inputs pin2 and pin3 are grounded through 1KE and single ended input is applied to pin 2. Pin 4 and pin 5 are usually connected together. In this way, the VCO output becomes an input to the phase detector. Locked output is taken from pin4. 

Free Running Frequency (fo):

                   When there is no input signal to the pin 2 PLL said to be in free running mode with it’s frequency determined by circuit elements Rt and Ct. Free running frequency is given by      

                                                                       

                        f0=0.3/RtCt

Where         

                    Rt is timing resistor and

                    Ct is timing capacitor.

Lock range (f_L):

                    Lock range of the PLL is the range of frequencies in which the already-locked PLL will remain in lock, and this is given by

                             fL=8F0/Vcc

Where      Vcc is supply voltage (+Vcc-(-vcc))   

Capture range (fc):

                      The capture range of the PLL is the range of frequencies on to which it will lock prior to being in lock. The capacitor Cc and internal resistor 3.6KE form a low-pass RC filter to remove the original frequencies, their harmonics, and the sum frequency and approximately given by

                                                                  

                                        fc = + [1/2P] Ö2Pf_L/3.6´10³ ´Cc

Where    f_L is Lock range

               Cc is filter capacitor

Equipment required:

                            

      1. PLL trainer board                         AET-26

      2. Dual trace oscilloscope               

      3. Digital frequency counters           PDC-16C-----2NO.S (Two no.s desirable for

                                                                   Satisfactory results)

      4.Digital multimeter.

Experimental Procedure:

 Free running Frequency: 

1. Switch on the trainer and measure the output of the regulated power supplies i.e.+12v and + 5v. These supplies are internally connected to the circuit, so no extra connections are required.
2.  Observe the output of the Square Wave generator-using Oscilloscope and measure the frequency range with the help of frequency counter. Frequency range should be around 1KHz to 10KHz.
3. Calculate the free-running frequency range of the circuit for different values of timing resistor Rt (to measure the Rt---Switch off the trainer and measure the Rt value using Digital multimeter between to given test points).

Connect 0.1uf capacitor (Cc) to the circuit and open the loop by short between pin 4 and pin 5. Measure the minimum and maximum free-running frequencies obtainable at the output of the PLL(pin4)by varying the pot. Compare your results with your calculation from step 3 (theoretical value). Simultaneously you can observe the output signal using CRO.

Lock range:

5.Calculate the lock range of the circuit for a 5KHz free-running frequency and record in table 1.2.

6.Connect pins 4,5 with the help of springs and adjust potentiometer to get a free-running frequency of 5KHz. Connect square wave generator output to the input of the PLL circuit. Provide a 5KHz square signal of 1 Vpp approximately (make this input frequency as close to the VCO frequency as possible).

6.Connect the frequency counters to the input and output of the PLL (you can also connect oscilloscope simultaneously).

7.Observe the input and output frequencies while slowly increasing the frequency of the square wave at the input. For some range output and input are equal (this known as locking and PLL said to be lock with the input signal. Record the frequency at which the PLL breaks lock (output frequency of the PLL will be around VCO frequency and in oscilloscope you will see a jittery waveform when it breaks lock instead of clean square wave). This frequency is called as upper end of the Lock range and record this as F2.

8.Beginning at 5KHz slowly decreases the frequency of the input and determine the frequency at which the PLL breaks lock on the low end and record it as F1.

9.Find lock range from F2-F1 and compare with the theoretical values from step 5.

Capture range:

10.Calculate the capture range of the circuit for a 5KHz free-running frequency(consider filter capacitor(Cc) is 0.1uf.

11.With the oscilloscope and counter still on pin4,slowly increase the input frequency from minimum (say 1KHz). Record frequency (as F3) at which the input and output frequencies of the PLL equal, this is known as lower end of the capture range.

12.Now keep input frequency at maximum possible (say 10KHz) and slowly reduce and record known as upper end of the capture range.

13.Find capture range from F4-F3 and compare it with the theoretical value (from step 10)

14.Repeat the step from 10 to 13 Cc value 0.2uf.

 

THATS IT THE EXPERIMENT ON PHASE LOCKED LOOP IS COMPLETED.......